Many logic circuits including complex logic functions such as decoders or logic gates with large numbers of inputs have been implemented in semiconductor devices including CMOS devices. When such logic systems are implemented in a full CMOS arrangement there has been a requirement for equal numbers of transistors of both P and N type. For this reason precharging techniques have been used in which an output node has been precharged by one or more precharging transistors of a first type and a plurality of inputs are fed to respective transistors of the opposite type and arranged so that the output node may remain charged or discharged depending on the particular input signals in relation to the logic function to be carried out by the circuit. By such precharging techniques it is possible to reduce the number of transistors required by almost one-half.
Simple two-phase clocking systems have been proposed for such precharging circuits such that the output node is precharged high or low during a first phase indicated by a first clock pulse and the value of the output is evaluated in a subsequent phase corresponding to a second clock pulse different from the first. In such arrangements the precharging occurs during a first clock pulse and evaluation of the output during a second clock pulse. Such schemes have been satisfactory provided the clock system remains satisfactory. If however the clock is stopped or a slow clock pulse is provided problems can arise during the second clock pulse or evaluation phase. In this event charge can be lost from the precharged output node due to the clock being stopped or running slow. This can result in an erroneous output from the output node.
It is an object of the present invention to provide a circuit and method of operation in which the benefit of using a reduced number of transistors is maintained while tolerating a period without an expected clock pulse.
It is a further object of the invention to control a precharging transistor in such a logic circuit so that during a phase when the output may be evaluated the precharging transistor is not switched completely off so that the output node is not erroneously discharged through excessive delays between successive clock pulses.